//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
//Date        : Mon Nov 25 22:54:07 2024
//Host        : Laptop-LZY running 64-bit major release  (build 9200)
//Command     : generate_target IP2_wrapper.bd
//Design      : IP2_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module IP2_wrapper
   (CLK_0,
    Q_0);
  input CLK_0;
  output [15:0]Q_0;

  wire CLK_0;
  wire [15:0]Q_0;

  IP2 IP2_i
       (.CLK_0(CLK_0),
        .Q_0(Q_0));
endmodule
